Endpoint Control 5
| RXS | RX Endpoint Stall - Read/Write 0 End Point OK |
| RXD | RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero |
| RXT | RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt |
| RXI | RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero |
| RXR | RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the host and device |
| RXE | RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured |
| TXS | TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared |
| TXD | TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 |
| TXT | TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt |
| TXI | TX Data Toggle Inhibit 0 PID Sequencing Enabled |
| TXR | TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID’s between the Host and device |
| TXE | TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured |